1. Field of the Invention
The present invention relates to an organic light emitting display, and more particular to a light emitting display and a driving method and circuit thereof, which may reduce the number of output lines in a data driver.
2. Description of the Related Technology
In general, an organic light emitting display electrically excites an organic compound such that it emits light. Circuits use voltage or current to drive an array of organic emitting cells so as to display images. Such an organic emitting cell often includes an anode formed of indium tin oxide (ITO), an organic thin film, and a cathode layer formed of metal.
The organic thin film has a multi-layer structure including an emitting layer (EML), an electron transport layer (ETL), and a hole transport layer (HTL) so as to maintain balance between electrons and holes and improve emitting efficiencies. The organic thin film may further include an electron injection layer (EIL) and a hole injecting layer (HIL).
Methods for driving organic emitting cells include a passive matrix method, and an active matrix method using thin film transistors (TFTs) or metal oxide semiconductor field effect transistors (MOSFETs). The passive matrix has cathode lines and anode lines crossing with each other, and selectively drives a cathode line and an anode line. The active matrix connects a TFT and a capacitor with each ITO pixel electrode to store a voltage according to the capacitor. The active matrix method is classified as either a voltage programming method or a current programming method according to signals supplied for storing the voltage at the capacitor.
The active matrix type of organic light emitting display includes a display panel, a data driving circuit, a scan driving circuit, and a timing controller. The scan driving circuit receives a scan drive control signal from the timing controller, generates a scan signal, and sequentially provides the scan signal to scan lines of the display panel.
That is, the scan driving circuit functions to sequentially generate the scan signal to be provided to the display panel in order to drive pixels included in the display panel.
FIG. 1 is a block diagram showing a conventional scan driving circuit. With reference to FIG. 1, the conventional scan driving circuit includes a plurality of stages ST1 to STn, which are connected to a start pulse SP input line. The plurality of stages ST1 to STn sequentially shifts a clock pulse in response to a start clock SP so as to generate output signals SO1 to Son. In this case, each of second to n-th stages ST2 to STn receives and shifts an output signal of a previous stage as a start pulse.
Accordingly, the stages generate output signals SO1 to SOn in such a way that the start pulse is sequentially shifted, and provide the output signals to a matrix pixel array.
FIG. 2 is a circuit diagram of a stage in the scan driving circuit shown in FIG. 1. FIG. 3 is an input/output waveform diagram of the stage shown in FIG. 2. Referring to FIG. 2 and FIG. 3, each stage uses a master-slave flip-flop. When a clock clk is at low level, such a flip-flop continues to receive an input and maintains a previous output.
In contrast, when the clock clk has a high logic level, the flip-flop maintains an input IN received when the clock clk is at the low level, and outputs the received signal even if the input IN changes.
In the aforementioned circuit, an inverter included in the flip-flop, shown in FIG. 2, has a problem in that a static current flows when an input thereof is at low level. Furthermore, in the flip-flop, the number of inverters having received a high-level input is the same number as that of inverters having received a low-level input. Accordingly, the static current constantly flows through half of the inverters in the flip-flop, thereby causing excessive power consumption.
In addition, FIG. 2 shows an embodiment of the inverter circuit. According to this embodiment the high level output of the inverter is determined according to the ratio of resistance values of first and second PMOS transistors M1 and M2. The low level output of the inverter is determined according to the threshold voltage of the first PMOS transistor M1.
Due to manufacturing variations, resistance and threshold parameters vary significantly from transistor to transistor. This is a significant problem because the transistors for organic light emitting displays often use transistors having high manufacturing variability. As a result, the performance of the circuit of FIG. 2 is uncertain. For example, threshold variation causes the low level output of each inverter to vary. As a result, when a low level output from a first inverter having an uncertain value is provided as the input to a second inverter, the second inverter may have a degraded high output level because the uncertain low value results in uncertain pull-up resistance in the first PMOS transistor of the second inverter.
Furthermore, in the inverter, when outputting a high level, a constant electric current flows through both the first and second PMOS transistors M1 and M2. This results in constant power consumption. Also, the constant electric current flowing in the second PMOS transistor M2 causes slower rise times for the inverter output signal.